Integrated circuits typically use various combinations of insulative materials, conductive materials, and semiconductive materials (including conductively doped semiconductive material). One type of conductive material which is utilized is elemental metals. In the context of this document, an “elemental metal” is defined to mean any one or more metal element(s) in element form, including any alloy of two or more metal elements. In many instances, it is desired to form a metal into electrical connection with a crystalline silicon substrate, for example conductively doped crystalline silicon. However, the physical contact of an elemental metal with a crystalline silicon substrate inherently creates undesired excessive electrical resistance between the two materials.
One common way of reducing this resistance is to form an interfacing silicide region at the junction or interface of the metal with the silicon. Thereby, a silicon-silicide-metal interfacing electrical connection is formed. One manner of forming the silicide is merely by heating the substrate with the two contacting layers to a suitable temperature for a sufficient period of time, typically in an inert atmosphere, to cause a reaction of metal and silicon to form the metal silicide. Alternately or in addition thereto, the deposition conditions for the metal material deposited over the silicon can be effectively high to impart a reaction of the depositing metal with the underlying silicon in situ during deposition. Regardless, the silicide which forms results from reaction of the metal with the underlying silicon substrate. The reaction is typically self-limiting such that further processing or exposure to temperature at some point stops resulting in silicide formation.
Integrated circuitry fabrication continues to strive to make ever denser and smaller electronic devices of the circuitry. One place where silicide contact structures are utilized is in the electrical connection of source/drain diffusion regions of field effect transistors with overlying conductive metal lines. As the device components get smaller and denser, it is highly desirable to precisely control the amount of silicide which is formed in such contacts, as well as in other devices where silicide interfaces between metal and silicon are desired to be formed. For example in some instances in present-generation processing, it is desirable to fabricate the silicide regions over the substrates to have thicknesses of from 50 Angstroms to 100 Angstroms. Further, it is expected that the thickness of silicide regions in later-generation processing will fall below 50 Angstroms. Regardless, the variation in thickness of silicide regions formed over a substrate using typical prior art processing has been found to be anywhere from 20 Angstroms to 25 Angstroms across the substrate. This variability is undesirable and constitutes a 20% to 25% thickness variation for desired 100 Angstroms thick silicide regions, and a 40% to 50% variation in thickness for desired 50 Angstroms thick silicide regions. It would be desirable to develop methods which enable tighter thickness control of silicide regions which are formed across a substrate, and particularly where the silicide regions being formed have thicknesses that are no greater than 100 Angstroms where the above problem particularly manifests.
While the invention was motivated in addressing the above described issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.